The present invention generally relates to the testing and placement of electronic components. More particularly, this invention relates to the burn-in and placement of integrated circuits (ICs or chips) on to a carrier substrate or circuit card which will ultimately be used in the manufacture of electronic devices, such as computers, or the like. Burn-in is a process of testing ICs by elevating their temperature and simultaneously performing electrical testing thereon. The present invention provides for simultaneous burn-in and direct chip attachment of multiple chips on to the carrier substrate. This direct chip attachment is a card fabrication process which results in permanent placement of ICs on the carrier substrate.
Conventional systems perform burn-in as a separate and distinct operation when compared with the circuit card fabrication process. For example, U.S. Pat. No. 4,881,591 describes a variable temperature oven having an associated computer for monitoring the electrical testing of the ICs, simultaneous with their exposure to the elevated temperatures of the oven. Burn-in boards are used to mount the ICs during the burn-in testing process. Further, U.S. Pat. No. 4,379,259 discuses a burn-in technique where ICs are mounted on PC storage cards which are then placed in an environmental chamber that elevates the temperature. The PC cards are constructed to isolate individual ICs which ensures burn-in of each chip. After burn-in, the PC cards are removed from the chamber and the ICs are removed from the card. The defective ICs are then separated from the good ICs, which are subjected to one by one short functional testing. U.S. Pat. No. 4,908,385 describes the electrical circuitry typically utilized for testing of ICS during burn-in. IBM Technical Disclosure Bulletin, Vol. 32, No 5A, October, 1989, "Non-Permanent Mounting Technique for Test and Burn-in of C4 Devices" describes a system in which a weight is applied to the top of the chip, making non-permanent electrical contact through the C4 solder ball with the vias of a text mount carrier substrate metallization.
Additionally prior art burn-in systems provide a global elevation in temperature within the test chamber, which may result in stress to the carrier substrate material. The conventional burn-in techniques address the problem of stress of the carrier substrate by using a carrier substrate for burn-in which will not ultimately be used in the product. Finally, the previously discussed stress to the carrier substrate is amplified due to the long time periods required by conventional systems to "ramp up" to burn-in temperatures.
Thus, it can be seen that conventional burn-in requires removal of the ICs after testing from a burn-in board, PC storage card, or the like. It would be advantageous to a circuit board manufacturer to have the ability to test ICs and fabricate a circuit board in a single process, thereby increasing efficiency and saving a great deal of time and overhead.